Electronic systems typically store data during operation in a memory device. In recent years, the dynamic random access memory (DRAM) has become a popular data storage device for such systems. Basically, a DRAM is an integrated circuit that stores data as binary, e.g., high and low, logic levels in a large number of cells. The data is stored in a cell as a charge on a capacitor located within the cell. Typically, a high logic level is approximately equal to the power supply voltage and a low logic level is approximately equal to ground.
The cells of a conventional DRAM are arranged in an array so that individual cells can be addressed and accessed. The array can be thought of as rows and columns of cells. Each row includes a word line that interconnects a gate of an access transistor of each cell on the row with a common control signal. Similarly, each column includes a bit line that is coupled to at most a source/drain region of one access transistor of a cell in each row. The capacitor is coupled between a second source/drain region of the access transistor and a common cell plate. Thus, the word and bit lines can be controlled so as to individually access each cell of the array.
To read data out of a cell, the capacitor of a cell is accessed by selecting the word line associated with the cell. An equilibration circuit equilibrates a complementary bit line pair that includes the bit line for the selected cell. The equilibration circuit effectively shorts the bit line pair to a reference supply. The voltage of the reference supply is typically midway between the high and low logic levels. Thus, conventionally, the bit lines are equilibrated to one-half of the power supply voltage, V.sub.CC /2. When the word line is activated for the selected cell, the capacitor of the selected cell discharges the stored voltage through the access transistor onto the bit line, thus changing the voltage on the bit line. When a high logic value is stored in the selected cell, the voltage on the bit line increases. Conversely, when a low logic level is stored in the selected cell, the voltage on the bit line decreases.
A sense amplifier detects and amplifies the difference in voltage on the bit line compared to the unchanged complementary bit line. The sense amplifier typically includes two main components: an n-sense amplifier and a p-sense amplifier. The n-sense amplifier includes a cross-coupled pair of n-channel transistors that drive the low bit line to ground. The p-sense amplifier includes a cross-coupled pair of p-channel transistors and is used to drive the high bit line to the power supply voltage.
An input/output device for the array, typically an n-channel transistor, is controlled to pass the voltage on the bit line for the selected cell to an input/output line for communication to, for example, a processor of a computer or other electronic system associated with the DRAM. In a write operation, data is passed from the input/output lines to the bit lines by the input/output device of the array for storage on the capacitor in the selected cell.
Conventionally, memory devices are fabricated as integrated circuits on a substrate, semiconductor wafer, or chip. Memory devices produced by conventional techniques may include one or more defects introduced during the production of the memory device. Such defects include, for example, shorted or open word lines, word line to digit line shorts, or defective access transistors and storage capacitors. To overcome these defects, manufacturers produce memory devices with redundant word and bit lines so that the defective parts can be logically, not physically, replaced. One problem with a short between a digit line and a word line is that the equilibration circuit provides a current path for the reference voltage source. The word line to bit line short effectively places the bit line at ground potential. When the equilibration circuit is turned on, a transistor in the equilibration circuit provides a path for current to ground from the reference voltage source.
Commonly assigned U.S. Pat. No. 5,235,550 issued to Paul S. Zagar (the "Zagar Patent"), which patent is incorporated herein by reference. The Zagar Patent provides one solution to this problem. The Zagar Patent describes the use of a current-limiting device, such as lightly doped polysilicon, or a long L transistor that is in an always-on state. This device is coupled between a reference voltage source and a number of equilibration circuits (see, e.g., FIG. 4 of the Zagar Patent) to limit the current provided from the reference voltage source to the equilibration circuit. This effectively reduces the current loss due to a word line to bit line short. Unfortunately, this current-limiting device also establishes a time constant which increases the time necessary to restore a digit line to an equilibration voltage level.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device with reduced susceptibility to current leakage from an equilibration voltage supply caused by a defective bit line.